Multi-Net Optimization of VLSI Interconnect (BOK)

Moiseev

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This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

Produktfakta

Språk Engelsk Engelsk Innbinding Innbundet
Utgitt 2014 Forfatter Moiseev
Forlag
Springer
ISBN 9781461408208
Antall sider 233 Leverandør Bertram Trading Ltd